The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More specifically, the present invention relates to a technique effectively applied to a CSP (chip size package) formed by applying a wafer process, i.e., a so-called wafer level CSP (WL-CSP) or a wafer process package, which is a scheme in which a packaging step is completed in a wafer state.
A scheme in which a packaging process (post-process) and a wafer process (pre-process) are integrated to each other to complete a packaging step in a wafer state, i.e., a technique so-called a wafer level CSP, has the following advantage. That is, since a packaging process is performed by applying a wafer process, the number of steps can be made considerably smaller than that of a conventional method in which a packaging process (post-process) is performed to each chip cut from a wafer. The wafer level CSP is also called a wafer process package (WPP).
In the wafer level CSP, a wiring layer in the CSP called an interposer for converting the pitch of bonding pads into the pitch of solder bumps can be replaced with rerouting layers formed on a wafer. For this reason, the wafer level CSP is expected to achieve the reduction in number of steps and the reduction in manufacturing cost of a CSP.
The wafer level CSP is described in, e.g., xe2x80x9cElectronic Packaging Technology 2000 Special Numberxe2x80x9d issued by Gijyutsu-chyosa-kai Corporation (issued on May 28, 2000) pp. 81 to 113, International Patent Publication No. WO99/23696, Japanese Patent Laid-Open Publication No. 2000-91339, Japanese Patent Laid-Open Publication No. 2000-138245, Japanese Patent Laid-Open Publication No. 2000-216253, and the like.
In the conventional method in which the packaging process (post-process) is performed to each chip cut from a wafer, a memory LSI such as DRAM (Dynamic Random Access Memory) has a redundancy function for repairing the defect area created in the wafer manufacturing process, which makes it possible to improve the production yield.
This is a defect repairing function to prevent the defect from spreading over the entire chip even if a defect occurs in a part of a circuit. Such defect repairing is performed in such a manner that rows and columns of spares (redundant circuit) are prepared in advance in a part of a circuit, and when an address signal enters the defective cell (defect bit) in the memory array, the rows and columns of spares are selected.
The replacement of the defect parts with the spare parts is made by cutting a fuse connected to an address switching circuit. In the cutting of the fuse, a current fusion cutting or a laser fusion cutting is generally used. Of the two, the laser fusion cutting is mainly employed because of the high degree of freedom in replacement program and advantages in area efficiency.
The fuse for repairing the defect is constituted of electrode wiring materials such as metal and polycrystalline silicon and is formed simultaneously in a step of forming a semiconductor element or a wiring (wafer process) on a wafer main surface. When the probe test performed in the final step of the wafer process detects the defect cell, the above-mentioned fuse is cut by means of laser to allocate the address corresponding to the defect cell to the redundant cell.
In ordinary cases, on the wafer surface, a surface protection layer termed as a passivation layer is formed on a metal wiring of the uppermost layer, and a resin layer such as polyimide is formed thereon. The passivation layer serves as a protection layer to prevent moisture from penetrating into a circuit from the wafer surface and is constituted of a fine inorganic dielectric layer such as a silicon oxide layer and a silicon nitride layer deposited by, for example, the plasma CVD method. In addition, the resin layer is formed with an aim to prevent the soft error due to the xcex1-ray, to prevent the damages to the chip surface due to the silicon filler in a resin (molding resin) for sealing the chip, and to relax the stress applied to the interface between the passivation layer and the molding resin.
The above-mentioned passivation layer and the resin layer are thickly formed with a thickness of micrometer (xcexcm) order. Therefore, for the defect repairing by cutting the fuse, the removal of the passivation layer and the resin layer on the fuse is required in advance of the probe test. Also, in the case where the fuse is formed of the relatively lower conductive layer, the interlayer dielectric layer lower than the passivation layer must be etched to reduce the thickness thereof.
For example, the process for removing the dielectric layer on the fuse proceeds as follows. First, a semiconductor element is formed on a main surface of a wafer, and subsequently, multiple layers of metal wirings are formed thereon. In this process, the fuse is formed in any one of a series of steps from forming the semiconductor element to forming the uppermost metal wiring.
Next, for the control of the thickness of the dielectric layer on the fuse to about 1 xcexcm, an opening is formed in the dielectric layer on the fuse by the dry etching with using a photo-resist layer as a mask, and thereafter, a passivation layer is formed on the uppermost metal wiring and in the bottom of the opening, and then, a polyimide layer is formed on the passivation layer. The passivation layer is formed by depositing a silicon nitride layer and a silicon oxide layer by the plasma CVD method at a temperature of 400xc2x0 C. to 500xc2x0 C. The polyimide layer is formed by the spin coating method. Thereafter, the baking process at a temperature of about 350xc2x0 C. is performed to cure the layer.
Subsequently, a photo-resist layer is formed on the polyimide layer, and the resin layer on the fuse is removed by the wet etching with using the photo-resist layer as a mask, thereby exposing the passivation layer. And simultaneously, a polyimide layer in the area used to form a bonding pad serving as an external connection terminal of a chip is removed to expose the passivation layer.
Next, after removing the photo-resist layer, the passivation layer on the fuse (the area in which the opening is formed in the dielectric layer) is removed by the dry etching with using the polyimide layer as a mask. And simultaneously, the passivation layer in the area used to form the bonding pad is removed to form the bonding pad.
Then, when the probe test performed in the final step of the wafer process detects the defect cell, the defect repairing is performed in such a manner that laser is irradiated to a predetermined fuse through the opening formed in the upper dielectric layer on the fuse in order to cut the fuse.
However, the inventors of the present invention have found out that when the defect repairing process as described above is applied to the conventional manufacturing process of the wafer level CSP, the following problems inevitably occur.
More specifically, in the case of the wafer level CSP, a rerouting layer is formed on the polyimide layer covering the wafer surface and a bump electrode serving as an external connection terminal is connected to one end of the rerouting layer after performing the probe test and the defect repairing. Therefore, the metal layer gets into the opening on the fuse during a step of forming the metal layer for the rerouting layer on the polyimide layer. Accordingly, a step of removing the metal layer in the opening by the use of etching solution is required in order to prevent the short circuit of the fuse cut by the laser via the metal layer. However, the corrosion of the fuse is caused if the etching solution is left in the opening.
Furthermore, in the manufacturing process of the wafer level CSP including the defect repairing process, openings for laser irradiation is left in the polyimide layer on the fuse. Therefore, when forming the rerouting layer on the polyimide layer, the rerouting layer must be arranged so as to avoid the openings. Consequently, the degree of freedom in the layout of the rerouting layer is reduced.
Also, in the conventional manufacturing process of the wafer level CSP, after the probe test and the defect repairing, steps of forming a rerouting layer on the polyimide layer and forming an uppermost protection layer made of polyimide layer on the rerouting layer are additionally performed. Therefore, if a heat treatment at a high temperature is performed during these steps, the characteristic of the memory cell is changed and the problem as that refresh times in each of the memory cells vary from each other occurs. As a result, even the chip determined to be good in the probe test may become defective.
An object of the present invention is to provide a technique capable of enhancing the degree of freedom in the layout of the rerouting layer in the wafer level CSP in which the defect repairing is performed by cutting a fuse.
Another object of the present invention is to provide a technique effectively preventing the corrosion of the fuse in the wafer level CSP in which the defect repairing is performed by cutting a fuse.
Another object of the present invention is to provide a technique capable of increasing the reliability of the wafer level CSP in which the defect repairing is performed by cutting a fuse.
The above and other objects and novel characteristic of the present invention will be apparent from the descriptions and accompanying drawings of this specification.
The typical aspects of the inventions disclosed in this application will be briefly described as follows.
The wafer level CSP in this invention includes: a plurality of memory cells formed on a main surface of a semiconductor chip; a plurality of fuses formed on the main surface of the semiconductor chip; a plurality of multi-layered first wirings formed in an upper layer of the plurality of memory cells; a plurality of internal connection terminals formed of the wiring in the same layer as the uppermost wiring of the plurality of first wirings; a passivation layer formed so as to cover the plurality of first wirings and the plurality of fuses and selectively exposing the plurality of internal connection terminals; a plurality of second wirings formed over the passivation layer, each having one end electrically connected to the internal connection terminal; an uppermost protection layer formed so as to cover the plurality of second wirings and selectively exposing the other ends of the plurality of second wirings; and a plurality of external connection terminals formed on the other ends of the plurality of second wirings, wherein at least a part of the plurality of second wirings are arranged over at least a part of the plurality of fuses.
A method of manufacturing the wafer level CSP in the present invention includes the steps of:
(a) forming a plurality of memory cells in a plurality of chip areas on a main surface of a wafer, forming a plurality of multi-layered first wirings in an upper layer of the plurality of memory cells, and forming a plurality of fuses in the plurality of chip areas during the step of forming the plurality of memory cells or the step of forming the plurality of first wirings;
(b) forming a passivation layer over the plurality of first wirings and the plurality of fuses, then removing parts of the passivation layers to expose the wiring in the same layer as the uppermost wiring of the plurality of first wirings, thereby forming a plurality of internal connection terminals;
(c) removing other parts of the passivation layers, thereby forming fuse openings over each of the plurality of fuses;
(d) after the step (b), conducting a probe test to detect the presence of defect cells, and irradiating laser to the fuse through a predetermined fuse opening of the plurality of fuse openings, thereby cutting the fuses by fusion when the probe test detects defect cells;
(e) after the step (d), forming an elastomer layer on the passivation layer, said passivation layer being formed also in the plurality of fuse openings;
(f) performing a heat treatment to the elastomer layer, thereby curing the elastomer layer;
(g) forming a plurality of second wirings having one ends electrically connected to the internal connection terminals over the elastomer layer, then forming an uppermost protection layer on the plurality of second wirings, and removing a part of the uppermost protection layer, thereby selectively exposing the other ends of the plurality of second wirings;
(h) performing a heat treatment to the uppermost protection layer, thereby curing the uppermost protection layer; and
(i) forming a plurality of external connection terminals at the other ends of the plurality of second wirings, then cutting the semiconductor wafer into chip areas, thereby obtaining semiconductor chips,
wherein the temperature of each of the heat treatments in the steps (f) and (h) is set so as not to change the predetermined characteristics of the plurality of memory cells.
A method of manufacturing the wafer level CSP in the present invention includes the steps of:
(a) forming a plurality of memory cells in a plurality of chip areas on a main surface of a wafer, forming a plurality of multi-layered first wirings in an upper layer of the plurality of memory cells, and forming a plurality of fuses in the plurality of chip areas during the step of forming the plurality of memory cells or the step of forming the plurality of first wirings;
(b) forming a passivation layer over the plurality of first wirings and the plurality of fuses, then removing parts of the passivation layers to expose the wiring in the same layer as the uppermost wiring of the plurality of first wirings, thereby forming a plurality of internal connection terminals;
(c) removing other parts of the passivation layers, thereby forming fuse openings over each of the plurality of fuses;
(d) after the step (b), conducting a probe test to detect the presence of defect cells, and irradiating laser to the fuse through a predetermined fuse opening of the plurality of fuse openings, thereby cutting the fuses by fusion when the probe test detects defect cells;
(e) forming a plurality of second wirings having one ends electrically connected to the internal connection terminals over the passivation layer, then forming an uppermost protection layer on the plurality of second wirings, and removing a part of the uppermost protection layer, thereby selectively exposing the other ends of the plurality of second wirings;
(f) performing a heat treatment to the uppermost protection layer, thereby curing the uppermost protection layer; and
(g) forming a plurality of external connection terminals at the other ends of the plurality of second wirings, then cutting the semiconductor wafer into chip areas, thereby obtaining semiconductor chips,
wherein the temperature of the heat treatment in the step (f) is set so as not to change the predetermined characteristics of the plurality of memory cells.